1. Field of the Invention
The present invention relates to a semiconductor memory device and, more particularly, to a semiconductor memory device in which a defective memory cell can be repaired after packaging.
2. Description of Related Art
Semiconductor memory devices include a memory cell array and a redundant memory cell array. When a defective memory cell is found in the memory cell array, the defective memory cell is replaced with a redundant memory cell in the redundant memory cell array, thereby repairing the defective semiconductor memory device.
Methods for replacing the defective memory cell with the redundant memory cell include replacing a word line connected to the defective memory cell with a redundant word line connected to the redundant memory cell and replacing a defective column selecting signal line connected to the defective memory cell with a redundant column selecting signal line connected to the redundant memory cell.
Of these, the method that replaces the column selecting signal line is used for replacing the defective memory cell with the redundant memory cell after packaging.
FIG. 1 is a schematic diagram illustrating a semiconductor memory device. The semiconductor memory device of FIG. 1 includes a memory cell array 10 having four (4) memory cell array blocks BK1 to BK4, a column decoder 12 having eight (8) decoders 12-1 to 12-8, a redundant column decoder 14 having four (4) decoders 14-1 to 14-4, a redundant enable signal generating circuit 16, and a block address decoder 18. The redundant enable signal generating circuit 16 includes redundant control signal generating circuits 16-11 and 16-12, a logical sum circuit 16-2, and a mode setting circuit 16-3. The four memory cell array blocks BK1 to BK4 include lower and upper blocks LBK1,UBK1 to LBK4,UBK4, respectively.
The memory cell array blocks BK1 to BK4 are selected in response to a 2-bit column address CA0/1 or CA0,CA1. Using the 2-bit column address CA0,CA1, the memory cell array block BK1 is selected when the column address CA0,CA1 is “00”, the memory cell array block BK2 is selected when the column address CA0,CA1 is “01” the memory cell array block BK3 is selected when the column address CA0,CA1 is “10”, and the memory cell array block BK4 is selected when the column address CA0,CA1 is “11”. The decoders 12-1 to 12-8 are electrically connected to the upper or lower memory cell array blocks LBK1 to UBK4, respectively. The decoders 12-1 to 12-8 decode the column addresses CA2˜9 or CA2 to CA9 to select a column selecting signal line. The decoders 12-1 to 12-8 are disabled when a redundant enable signal REN is activated and block selecting signals bk1 to bk4 are activated. For example, when the redundant enable signal REN is activated and the block selecting signal bk1 is activated, the decoders 12-1 are disabled. The decoders 14-1 to 14-4 are enabled to select redundant column selecting signal lines RCSL1 to RCSL4, respectively, when the redundant enable signal REN and the block selecting signals bk1 to bk4 are activated. The redundant column selecting signal lines RCSL1 to RCSL4 have line pairs RCSL11,RCSL12 to RCSL41,RCSL42 which are divided respectively for lower and upper blocks LBK1,UBK1 to LBK4,UBK4 of the memory cell array blocks BK1 to BK4. The mode setting circuit 16-3 receives a code CODE applied from an external portion to generate program column addresses PCA09 or PCA0 to PCA9 in response to a mode setting command MRS during a mode setting operation. The redundant control signal generating circuits 16-11 and 16-12 are programmed to defective column addresses in response to the program column addresses PCA0 to PCA9 during the mode setting operation. The redundant control signal generating circuits 16-11 and 16-12 generate redundant control signals REN1 and REN2 when the column addresses CA0 to CA9 including, CA0/1 and CA2 to CA9, applied from an external portion during a normal operation, e.g., a read operation, a write operation, etc., are identical to the programmed column addresses PCA0 to PCA9, respectively. The logical sum circuit 16-2 logically sums the redundant control signals REN1 and REN2 to generate the redundant enable signal REN. The block address decoder 18 decodes the column address CA0/1 to generate the block selecting signals bk1 to bk4.
The semiconductor memory device selects two lines of each of the line pairs RCSL11,RCSL12 to RCSL41,RCSL21 together when the decoders 41-1 to 14-4 select the redundant column selecting signals RCSL1 to RCSL4 and the redundant column selecting signals lines RCSL1 to RCSL4 are respectively selected.
In the semiconductor memory device of FIG. 1, when a defect occurs in a memory cell MC1 between the column selecting signal line CSL1 of the lower block LBK1 of the memory cell array block BK1 and a word line WL, the defective memory cell MC1 should be replaced with a redundant memory cell RMC1. If it is assumed that all column addresses CA0 to CA9 of the defective memory cell MC1 are “0” the mode setting circuit 16-3 receives the code CODE to generate the program column addresses PCA0 to PCA9 all of which are “0” in response to the mode setting command MRS. The redundant control signal generating circuit 16-11 is programmed to “0” in response to the program column addresses PCA0 to PCA9 during the mode setting operation and generates the redundant control signal REN1 when the column addresses CA0 to CA9 all of which are “0” are applied during the normal operation. The logical sum circuit 16-2 activates the redundant enable signal REN in response to the redundant control signal REN1. The block address decoder 18 decodes the column address CA0,CA1 of “00” to generate the block selecting signal bk1 of “1”. The column address decoders 12-1 and 12-2 are disabled, whereas the redundant column address decoder 14-1 is enabled. The column address decoders 12-3 to 12-8 are enabled, and the redundant column address decoders 14-2 to 14-4 are disabled. As a result, the defective column selecting signal line CSL1 of the lower and upper blocks LBK1 and UBK1 of the memory cell array block BK1 is replaced with the redundant column selecting signal line RCSL11, whereby the defective memory cell MC1 is replaced with the redundant memory cell RMC1. At this time, a memory cell MC2 which is not defective is also replaced with a redundant memory cell array RMC2. Accordingly, the defective semiconductor memory device is repaired.
When a defect additionally occurs in a memory cell MC2 of the upper block UBK1 of the memory cell array block BK1, it is difficult to repair the defect. That is, since the redundant column selecting signal line RCSL12 is already used to replace the column selecting signal line CSL1 of the upper block UBK1 of the memory cell array block BK1, there is no redundant column selecting signal line for replacing the column selecting signal line CSL2 connected to the defective memory cell MC3.
To provide support for repairing MC2, an additional redundant column selecting signal line may be arranged per each memory cell array block. In this case, the layout area size of the memory cell array and device manufacturing costs are increased.